Today, a semiconductor memory is used in various commercial products, such as a main memory of both large-sized computer and personal computer, a home electric appliance, a cellular phone and the like. As a kind of semiconductor memory, a volatile DRAM (Dynamic RAM), a volatile SRAM (Static RAM), a nonvolatile MROM (Mask ROM), a nonvolatile flash EEPROM (flash memory) and the like have come out as a device product. Especially, the DRAM, in spite of the volatile memory, is superior to another memory from view points of a lower cost and a higher speed. For example, a cell area of the DRAM is ¼ as compared with that of the SRAM and a speed of the DRAM as device performance is higher than that of the flash memory. Therefore, the DRAM largely occupies in the present semiconductor memory market. On the other hand, the flash memory is rewritable and nonvolatile, and power supplied to the flash memory can be switched off, however, rewriting number (W/E) of the flash memory is approximately 106 and writing time of the flash memory takes approximately micro seconds. Furthermore, the flash memory has to be applied to high voltage (12V-22V) in a writing process. These shortages lead the flash memory to fewer commercial products as compared with the DRAM.
On the other hand, a nonvolatile ferroelectric memory using a ferroelectric capacitor was proposed in 1980. Since then, as the nonvolatile ferroelectric memory has advantages such as nonvolatile property, W/E number being approximately 1012, a reading time and a writing time being nearly the same as those of the DRAM, an operation in 3V-5V and the like, it has been developed by many electronics manufacturers. The nonvolatile ferroelectric memory has capability of replacing all the commercial products in the memory market.
Conventionally, for example, as J. T. Evans et al., described in “An experimental 512k-b nonvolatile memory with ferroelectric cell”, IEEE Journal Solid-State Circuit, vol. 23, No. 5, pp. 1171-1175, October 1988, the ferroelectric memory cell is constituted of one cell transistor and one ferroelectric capacitor. The cell transistor and the ferroelectric capacitor are connected in series. One memory cell is arranged at two intersections of a word line and a bit line in a folded-bit-line structure of a conventional ferroelectric memory. In the structure, the minimum size of the memory cell is 2F×4F=8F2, where a width of an interconnection and a space between interconnections is F. As a result, the miniaturization of the cell size has a restriction.
Moreover, in the conventional memory cell structure, plate lines are divided into each word line and are individually driven in order to prevent destruction of polarization information of a non-selected cell in the ferroelectric capacitor. As a plurality of the ferroelectric capacitors are connected to each of the plate lines along the word line direction, the load capacity of the ferroelectric capacitor become large. Furthermore, as a layout pitch of a plate line drive circuit becomes severe as comparable as the layout pitch of the word line, the layout size of the plate line drive circuit can not be designed comparatively large. For the reason mentioned above, in the conventional ferroelectric memory, delay of the voltage applied to the upper and the lower sides of the plate lines becomes large. As a result, there was a shortage that an operation speed of the ferroelectric memory becomes slow.
In order to cope with such shortages, authors disclose a ferroelectric memory, for example, in Japanese Patent Publications, such as Japanese Patent Publication (Kokai) No. H10-255483, Japanese Patent Publication (Kokai) No. H11-177036, and Japanese Patent Publication (Kokai) No. 2000-22010. The ferroelectric memory can realize three points, (1) a small ferroelectric memory cell of 4F2 size (2) a plane transistor being simply fabricated (3) a high speed random access function with versatility. By applying such technology to the ferroelectric memory, the ferroelectric memory cell of a minimum size of 4F2 by using the plane transistor can be realized.
However, realization of the memory cell having smaller size than 4F2 is principally difficult in the ferroelectric memory, even if these techniques are applied. Furthermore, a multiple value NAND flash memory can perform R/W of data at high speed than the conventional NAND flash memory and substantially realize a cell size below 4F2 by memorizing multiple value information in one cell. Therefore, realization of the ferroelectric memory cell exceeding the multiple value NAND flash memory in lower cost is difficult.
On the other hand, there exists a ferroelectric memory constituted of three-dimensional structure. For example, T. Nishihara et al. demonstrated that a transistor is formed on a silicon substrate and a ferroelectric capacitor is stacked in layer in “A quasi-matrix ferroelectric memory for future silicon storage”, IEEE Journal Solid-State Circuit, vol. 27, No. 11, pp. 1479-1484, November 2002. The ferroelectric memory having a small size and a large capacity is constituted of a plurality of ferroelectric capacitors stacked in layer.
In the conventional method as described above, the ferroelectric capacitors are simply disposed without being connected by the transistor. When data are both writing in and reading out to/from the ferroelectric capacitor, unnecessary voltage over ⅓ is applied to adjacent non-selective ferroelectric capacitor. This is so called a disturb phenomenon being generated in the non-selective ferroelectric capacitor. This is a serious problem as degradation of a stable operation on the ferroelectric memory. Therefore, the ferroelectric memory has had a difficult problem for practical realization. Accordingly, fabricating of a ferroelectric capacitor being strongly prevented from the disturb phenomenon has been developed as a main subject.
As mentioned above, practical realization of a cell size being smaller than 4F2 is difficult in the conventional ferroelectric memory. Further, a three-dimensional ferroelectric memory stacked in layer has a difficulty for practical realization in accordance with the disturb phenomenon.